CYRS1542AV18
CYRS1544AV18
Write Operations
Functional Overview
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
The CYRS1542AV18, and CYRS1544AV18 are synchronous
pipelined burst SRAMs with a read port and a write port. The read
port is dedicated to read operations and the write port is
dedicated to write operations. Data flows into the SRAM through
the write port and flows out through the read port. These devices
multiplex the address inputs to minimize the number of address
pins required. By having separate read and write ports, the
QDR II+ completely eliminates the need to turnaround the data
bus and avoids any possible data contention, thereby simplifying
system design. Each access consists of two 18-bit data transfers
in the case of CYRS1542AV18, and two 36-bit data transfers in
the case of CYRS1544AV18 in one clock cycle.
When deselected, the write port ignores all inputs after the
pending write operations are complete.
Byte Write Operations
This device operates with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to VSS then the device behaves in QDR I mode with a read
latency of one clock cycle.
Byte write operations are supported by the CYRS1542AV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate BWS input during the data portion of a
write latches the data being presented and writes it into the
device. Deasserting the byte write select input during the data
portion of a write enables the data stored in the device for that
byte to remain unaltered. This feature can be used to simplify
read, modify, or write operations to a byte write operation.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the output clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (K and K).
Concurrent Transactions
The read and write ports on the CYRS1542AV18 operate
independently of one another. As each port latches the address
inputs on different clock edges, you can read or write to any
location, regardless of the transaction on the other port. You can
start reads and writes in the same clock cycle. If the ports access
the same location at the same time, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CYRS1542AV18 is described below. The same basic
descriptions also apply to CYRS1544AV18.
Read Operations
The CYRS1542AV18 is organized internally as two arrays of
2 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next two K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
K as the output timing reference. On the subsequent rising edge
of K, the next 18-bit data word is drive onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the output
clock (K and K).
Depth Expansion
The CYRS1542AV18 has a port select input for each port. This
allows for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting one port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
When the read port is deselected, the CYRS1542AV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive input clock (K). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Document Number: 001-60006 Rev. *I
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