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IZ74LVU04

型号:

IZ74LVU04

描述:

六反相器[ HEX INVERTER ]

品牌:

INTEGRAL[ INTEGRAL CORP. ]

页数:

6 页

PDF大小:

141 K

IN74LVU04  
HEX INVERTER  
The 74LVU04 is a low-voltage, Si-gate CMOS device and is  
pin compatible with the 74HCU04.  
The 74LVU04 is a general purpose hex inverter. Each of the  
six  
N SUFFIX  
PLASTIC  
inverters is a single stage with unbuffered outputs.  
14  
Wide Operating Voltage: 1.0÷5.5 V  
1
D SUFFIX  
SOIC  
Optimized for Low Voltage applications: 1.0÷3.6 V  
Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V  
Low Input Current  
14  
1
ORDERING INFORMATION  
IN74LVU04N  
IN74LVU04D  
IZ74LVU04  
Chip  
Plastic  
SOIC  
TA = -40° ÷ 125° C for all  
packages  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
FUNCTION TABLE  
Input  
Output  
PIN 14 =VCC  
PIN 7 = GND  
A
L
Y
H
L
H
1
IN74LVU04  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 ÷ +7.0  
±20  
Unit  
V
mA  
mA  
mA  
VCC  
DC supply voltage (Referenced to GND)  
DC input diode current  
IIK *1  
2
IOK  
*
DC output diode current  
±50  
IO *3  
ICC  
DC output source or sink current  
-bus driver outputs  
±25  
DC  
VCC  
current  
for  
types  
with  
mA  
mA  
mW  
±50  
±50  
- bus driver outputs  
IGND  
PD  
DC GND current for types with  
- bus driver outputs  
Power dissipation per package, plastic  
750  
500  
DIP+  
SOIC  
package+  
Tstg  
TL  
Storage temperature  
-65 ÷ +150  
°C  
°C  
Lead temperature, 1.5 mm from Case for  
10 seconds (Plastic DIP ), 0.3 mm (SOIC  
Package)  
260  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C  
SOIC Package: : - 8 mW/°C from 70° to 125°C  
*1: VI < -0.5V or VI > VCC+0.5V  
*2: Vo < -0.5V or Vo > VCC+0.5V  
*3: -0.5V < Vo < VCC+0.5V  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
DC Supply Voltage (Referenced to  
GND)  
Min  
1.0  
Max  
5.5  
Unit  
V
VIN, VOUT  
TA  
DC Input Voltage, Output Voltage  
(Referenced to GND)  
0
VCC  
V
Operating Temperature, All Package  
Types  
-40  
+125  
°C  
tr, tf  
Input Rise and Fall  
Time  
0
0
0
0
500  
200  
100  
50  
ns  
1.0 VVCC <2.0 V  
2.0 VVCC <2.7 V  
2.7 VVCC <3.6 V  
3.6 VVCC 5.5 V  
This device contains protection circuitry to guard against damage due to high static  
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage  
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and  
V
OUT should be constrained to the range GND(VIN or VOUT)VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or  
VCC). Unused outputs must be left open.  
2
IN74LVU04  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Guaranteed Limit  
Test  
VCC,  
V
25°C  
-40°C ÷ 85°C  
-40°C ÷  
125°C  
Symbol  
VIH  
Parameter  
Unit  
V
Conditions  
min max min max min max  
High-Level  
Input Voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
1.0  
1.6  
2.4  
2.4  
2.4  
3.6  
4.4  
-
1.0  
1.6  
2.4  
2.4  
2.4  
3.6  
4.4  
-
1.0  
1.6  
2.4  
2.4  
2.4  
3.6  
4.4  
-
VIL  
Low  
-Level  
0.2  
0.4  
0.5  
0.5  
0.5  
0.9  
1.1  
-
0.2  
0.4  
0.5  
0.5  
0.5  
0.9  
1.1  
-
0.2  
0.4  
0.5  
0.5  
0.5  
0.9  
1.1  
-
V
V
Input Voltage  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VOH  
High-Level  
VI = VIH or 1.2 1.05  
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
Output Voltage  
VIL  
2.0 1.85  
-
-
-
I0=-100 µA 2.7 2.55  
3.0 2.85  
-
-
-
-
-
-
3.6 3.45  
-
-
-
4.5 4.35  
-
-
-
5.5 5.35  
-
-
-
VI = VIH or  
VIL  
3.0 2.48  
-
2.40  
-
2.20  
-
I0=-6.0 mA  
VI = VIH or  
VIL  
4.5 3.70  
-
3.60  
-
3.50  
-
I0=-12 mA  
VOL  
Low-Level  
VI = VIH or 1.2  
-
-
-
-
-
-
-
-
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.33  
-
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.40  
-
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.50  
V
Output Voltage  
VIL  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
I0=100 µA  
VI = VIH or 3.0  
VIL  
I0=6.0 mA  
VI = VIH or 4.5  
VIL  
-
-
0.40  
-0.1  
-
-
0.55  
-1.0  
-
-
0.65  
-1.0  
I0=12 mA  
VI=0 V  
IIL  
Low-Level  
5.5  
µA  
Input Leakage  
Current  
DC ELECTRICAL CHARACTERISTICS (continuation)  
3
IN74LVU04  
Guaranteed Limit  
Test  
VCC,  
V
25°C  
-40°C ÷ 85°C  
-40°C ÷  
125°C  
Symbol  
IIH  
Parameter  
Unit  
Conditions  
min max min max min max  
High-Level  
VI= VСС  
5.5  
-
0.1  
4.0  
-
-
1.0  
20  
-
1.0  
Input Leakage  
Current  
ICC  
Quiescent  
VI=0 В or 5.5  
-
-
40  
µA  
Supply Current VСС  
(per Package)  
IO = 0 µA  
ICC1  
Additional  
VI = VСС  
0.6V  
-
2.7  
3.6  
-
-
0.2  
0.2  
-
-
0.5  
0.5  
-
-
-
0.85  
0.85  
mA  
Quiescent  
Supply Current  
on input  
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 k)  
Guaranteed Limit  
Test  
VCC  
V
25°C  
-40°C ÷  
85°C  
-40°C ÷  
125°C  
Symbol  
Parameter  
Conditio  
ns  
Unit  
ns  
min max min max min max  
tPHL  
Propagation  
VI=0 V or 1.2  
2.0  
-
-
-
-
-
70  
22  
16  
13  
11  
-
-
-
-
-
80  
26  
19  
15  
13  
-
-
-
-
-
100  
31  
(tPLH) Delay, Input A V1  
to Output Y tLH = tHL 2.7  
23  
(Figure 1 )  
=2.5 ns 3.0  
18  
СL = 50 4.5  
16  
pF  
RL = 1  
kΩ  
CI  
Input  
5.5  
-
7.0  
-
-
-
-
pF  
pF  
Capacitance  
CPD  
Power Dissipation Capacitance (Per  
ТА=25°С, VI=0V or VCC  
Inverter)  
to  
36  
Used  
determine  
the  
no-load  
dynamic  
power  
consumption:  
PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz)  
(CLVCC2fo) – sum of the outputs  
4
IN74LVU04  
tHL  
tLH  
V1  
0.9  
0.9  
Input А  
VX  
VX  
0.1  
GND  
0.1  
tPHL  
tPLH  
VOH  
VOL  
Output Y  
VY  
VY  
VX=0.5 VCC  
Figure 1. Switching Waveforms  
VCC  
VI  
VO  
Termination resistance RT  
should be equal to ZOUT of pulse  
generators  
DEVICE  
UNDER  
PULSE  
GENERATOR  
TEST  
RT  
RL  
CL  
Figure 2. Test circuit  
5
IN74LVU04  
CHIP PAD DIAGRAM IZ74LVU04  
1.33  
±0.03  
11  
13  
10  
12  
09  
08  
07  
14  
01  
02  
04  
05  
06  
03  
Chip marking  
IN74LVU04  
(x=0.130; y=0.130  
)
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)  
Thickness of chip 0.46 ± 0,02 mm  
PAD LOCATION  
Pad No  
Symbol  
X
Y
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
A1  
0.130  
0.130  
0.381  
0.616  
0.881  
1.116  
1.115  
1.115  
1.115  
0.804  
0.569  
0.378  
0.143  
0.130  
0.463  
0.230  
0.126  
0.126  
0.126  
0.126  
0.631  
0.846  
1.181  
1.194  
1.194  
1.194  
1.194  
0.813  
Y1  
A2  
Y2  
A3  
Y3  
GND  
Y4  
A4  
Y5  
A5  
Y6  
A6  
VCC  
6
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